module udp_ctrl(
    input       clk          ,
    input       rst_n        ,
    input       key_pulse    ,
    input       udp_rx_done  ,
    output reg  tx_start    
    );

// 测试用
reg key_pulse_t;
wire key_pulse_pos;
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        key_pulse_t <= 1'd0;
    end
    else
        key_pulse_t <= key_pulse;
end
assign key_pulse_pos = ~key_pulse_t & key_pulse;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        tx_start <= 1'd0;
    end
    else begin
        tx_start <= 1'd0;
        if(udp_rx_done)         // 发数据
            tx_start <= 1'd1;
        else if(key_pulse_pos)       
            tx_start <= 1'd1; 
    end
end

endmodule
